Field of the Invention
The invention relates to a scan cell of an integrated circuit, and more particularly to a scan cell having an asymmetric skew in normal/scan mode.
Description of the Related Art
After integrated circuit (IC) chips are manufactured, tests are performed on the chips to verify whether the chips are normal. At present, Design-For-Testability (DFT) mechanisms for an IC chip include utilizing a plurality of scan cells to perform manufacturing tests on the IC chip.
In the design process for an IC chip, various clock trees are inserted into the circuit design of the IC chip, and the physical placement is adjusted accordingly. Clock adjustment is then performed on the circuit. In the process of designing and inserting the clock tree, clock skew is important to consider. All sequential logic units (e.g. registers and latches) of the circuit need a clock signal. However, the time of the clock signal arriving at different sequential logic units is different because the path from the clock source to each sequential logic unit is different. This time difference is also called a clock skew. There are various factors leading to a clock skew, including the path length difference among different units, the load number and size difference, the difference caused by OCV (on-chip variation), etc. OCV includes manufacturing technical variation, operational voltage variation, ambient temperature variation, etc.